The recent trend of miniaturizing electrical and electronic products in accordance with rapid advancement in techniques induces high integration and microminiaturization of the electronic products. Owing to such a trend, studies on surface mounting technology (SMT) for mounting highly integrated and miniaturized surface mounted devices (SMD) on a printed circuit board (PCB) are accelerated. The surface mounted device (SMD) refers to an element directly attached and soldered to a pattern without drilling a hole on the PCB or a ceramic substrate, and the SMD includes a chip resistor, a chip capacitor, a chip transistor and the like.
One of the technical requirements related to light, thin, short and small electronic products is mounting chips or wires in a small area at a high density. To satisfy such a requirement, multi-layer packages of packaging semiconductor chips and wires in a multi-layer structure have been proposed. Such a multi-layer package forms a plurality of via holes on at least one upper layer stacked on a base layer, fills a conductive material into the via holes, and electrically connects the conductive material to signal lines formed on the top and bottom using a solder, a stud or the like. A conventional via hole is formed in the shape of a hole having the same inner diameter.
However, after the via holes are formed in the outer periphery of a PCB substrate, a routing process of cutting the outer periphery is performed to form the PCB substrate in the shape of a product size, and a bur phenomenon of uncleanly cutting and drooping the PCB substrate and a number of plating defects occur on the surface of the via holes in the routing process.